1. Field of the Invention
The present invention relates to phase locked loops (PLL's) and more particularly to PLL's including a two-input/two-output phase comparator, the first output providing a signal when the first input is in phase advance with respect to the second, and the second output providing a signal when the second input is in phase advance with respect to the first input.
2. Discussion of the Related Art
FIG. 1 is a simplified diagram of an exemplary conventional so-called "charge-pump" PLL.
A phase comparator (PFD) 10 receives at a first input a logic signal Fext, and at a second input a logic signal Fvco provided by a voltage-controlled oscillator (VCO) 12. Comparator 10 is generally sensitive to the falling edges of signals Fext and Fvco. A charge-pump includes two current sources 14, 15 of equal value I, for charging or discharging capacitors that may be included in a filter 17. Sources 14 and 15 are disposed in series between a high voltage Vcc and a low voltage Vss and are respectively controlled by an UP output and a DOWN output of the phase comparator 10. The junction between sources 14 and 15 is connected to the control input of oscillator 12 and to filter 17 which is connected to a reference voltage G, such as ground. Filter 17 generally includes an integration capacitor C1 disposed in series with a correction cell including a resistor R and a capacitor C2 interconnected in parallel.
The UP output of phase comparator 10 provides pulses (UP pulses) having a duration equal to the phase advance of signal Fext with respect to signal Fvco. The DOWN output provides pulses (DOWN pulses) having a duration equal to the phase lag of signal Fext with respect to signal Fvco. Thus, the capacitors of filter 17, especially capacitor C1 which has a high value with respect to capacitor C2, are progressively charged or discharged in accordance with the phase relation between signals Fext and Fvco. Voltage Vc across filter 17, which varies as a function of this phase relation, corrects the frequency of VCO 12 in order to catch-up the phase error of signal Fvco. The correction cell R, C2 provides, during each rising edge of an UP or DOWN pulse, a voltage peak to briefly overcorrect the VCO 12.
FIG. 2 shows signals Fext, Fvco, UP and DOWN corresponding to an exemplary case. For the sake of simplification of the drawings, signals Fext and Fvco are represented in the form of pulses having a practically zero duration. Signal Fext is represented as having a constant frequency. Each pulse of signal Fext is marked E.sub.n ; the corresponding pulse of signal Fvco is marked V.sub.n, index n being an integer representing the pulse rank.
At a time t.sub.0, a pulse V.sub.0 of signal Fvco is provided before the corresponding pulse E.sub.0 of signal Fext. Comparator 10 then detects a phase advance of signal Fvco with respect to signal Fext and provides an active DOWN pulse from pulse V.sub.0 up to pulse E.sub.0, which causes the frequency of signal Fvco to decrease. The next pulse V.sub.1 is still in advance with respect to pulse E.sub.1. Then, a new DOWN pulse occurs and causes the frequency of signal Fvco to decrease again, and so forth. This first step during which DOWN pulses are generated is continued until a phase coincidence is obtained between pulses E.sub.i-1 and V.sub.i-1 at a time t.sub.1.
Then, a second step during which UP pulses are generated is initiated. From the timing of pulses E.sub.i and Vi, it is determined that signal Fvco is in phase lag with respect to signal Fext. The PLL compensates for this phase lag by increasing the frequency of signal Fvco responsive to the generated UP pulses, until signal Fvco is again in phase advance with respect to signal Fext.
The two preceding steps alternatively occur until signals Fext and Fvco are in synchronism. Before reaching such synchronism, the frequency of signal Fvco oscillates about the frequency of signal Fext.
FIG. 3A shows the waveform of the frequency variation of signal Fvco in the case of a phase shift of signal Fext after signals Fext and Fvco are initially in synchronism. This situation corresponds for example to that of FIG. 2 and may be caused by a missing pulse (E.sub.00 in FIG. 2) from signal Fext. In the case of a missing pulse E, the PLL "considers" the situation as though signal Fvco was in a phase advance of one period.
At time t.sub.0 the phase shift of signal Fext occurs. From time t.sub.0, the frequency of signal Fvco starts oscillating about the frequency of signal Fext and slowly tends to this frequency. Times t.sub.0 and t.sub.1 of FIG. 3 correspond to times t.sub.0 and t.sub.1 of FIG. 2.
FIG. 3B illustrates the frequency waveform of signal Fvco when the frequency of signal Fext shifts at a time t.sub.0 up to an upper value. From time t.sub.0, the frequency of signal Fvco increases, exceeds the new frequency of signal Fext, and then oscillates about the new frequency and slowly tends up to the new frequency.
If, in FIG. 3B, time t.sub.0 corresponds to a starting of the loop, the situation of FIG. 2 can be found, that is, signal Fvco is in phase advance with respect to signal Fext but is at a lower frequency. Then, as shown in dashed lines, the frequency of signal Fvco starts decreasing, that is, it initially varies in a direction opposite to the desired direction.
It can be appreciated that the PLL tends to rapidly compensate for the phase error between signals Fext and Fvco by modifying the frequency of signal Fvco at each pulse, with the resulting drawback of causing the frequency of signal Fvco to oscillate. The oscillation duration and the amplitude thereof increase as the initial phase error increases. A phase shift or a missing pulse substantially disturbs the loop, even if signals Fext and Fvco are in synchronism.
The frequency of signal Fvco may not even converge in the direction of signal Fext during a specific perturbation or if some of the components are incorrectly selected. The components of filter 17 must be carefully chosen so as to make trade-offs between stability and speed of synchronization.
Another drawback of the PLL's such as the one of FIG. 1 is that capacitors, especially capacitor C.sub.1, and resistor R of filter 17 generally have high values and must be external to an integrated circuit including the other elements of the PLL.